drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled

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CI test results/further experiments show that the workaround added in

commit 573d7ce4f6 ("drm/i915/adlp: Add workaround to disable CMTG clock gating")

can be applied only while DPLL0 is enabled. If it's disabled the
TRANS_CMTG_CHICKEN register is not accessible. Accordingly move the WA
to DPLL0 HW state sanitization and enabling.

This fixes an issue where the WA won't get applied (and a WARN is thrown
due to an unexpected value in TRANS_CMTG_CHICKEN) if the driver is
loaded without DPLL0 being enabled: booting without BIOS enabling an
output with this PLL, or reloading the driver.

While at it also add a debug print for the unexpected register value.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210802190148.2099625-1-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2021-08-02 22:01:48 +03:00

parent 82929a2140

commit 233624e0d5

2 changed files with 33 additions and 19 deletions

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18

drivers/gpu/drm/i915/display/intel_display.c

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34

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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