clk: renesas: r9a09g011: Add eth clock and reset entries

Browse source

Add ethernet clock/reset entries to CPG driver.

Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

...

This commit is contained in:

Phil Edworthy 2022-05-04 15:54:46 +01:00 • committed by Geert Uytterhoeven

parent 1dd65bb086

commit 23426d1be3

1 changed files with 9 additions and 5 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

14

drivers/clk/renesas/r9a09g011-cpg.c

View file