drm/i915/hdmi: C20 computed PLL frequencies

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Use algorithm to generate HDMI C20 PLL clock frequencies.

v2: checkpatch fixes

BSPEC: 64568
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
[mattrope: Wrapped one overly long line]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230515231725.3815199-3-clinton.a.taylor@intel.com

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Clint Taylor 2023-05-15 16:17:25 -07:00 • committed by Matt Roper

parent cb7b04c83e

commit 234fcb978f

2 changed files with 137 additions and 6 deletions

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90

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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53

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

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