ASoC: adau1701: allow configuration of PLL mode pins

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The ADAU1701 has 2 hardware pins to configure the PLL mode in accordance
to the MCLK-to-LRCLK ratio. These pins have to be stable before the chip
is released from reset, and a full reset cycle, including a new firmware
download is needed whenever they change.

This patch adds GPIO properties to the DT bindings of the Codec, and
implements makes the set_sysclk memorize the configured sysclk.

Because the run-time parameters are unknown at probe time, the first
firmware download is postponed to the first hw_params call, when the
driver can determine the mclk/lrclk divider. Subsequent downloads
are only issued when the divider configuration changes.

Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

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Daniel Mack 2013-06-24 16:31:30 +02:00 • committed by Mark Brown

parent de9fc724da

commit 2352d4bf43

2 changed files with 104 additions and 7 deletions

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6

Documentation/devicetree/bindings/sound/adi,adau1701.txt

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105

sound/soc/codecs/adau1701.c

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