ASoC: rockchip: i2s: change bclk and lrck according to sample rates

Browse source

This patch sets the dividers autonomously.

when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.

As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Caesar Wang 2015-11-06 19:38:14 +08:00 • committed by Mark Brown

parent 8005c49d9a

commit 2458c37779

1 changed files with 23 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

23

sound/soc/rockchip/rockchip_i2s.c

View file