serial: tegra: Correct delay after TX flush

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For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 32 UART clock periods for the flush
to propagate otherwise TX data could be post. Add a helper function
to wait for N UART clock periods and update delay following FIFO
flush to be 32 UART clock cycles.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Jon Hunter 2015-05-05 15:17:52 +01:00 • committed by Greg Kroah-Hartman

parent 7a7a7e6d9b

commit 245c0278ab

1 changed files with 22 additions and 2 deletions

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drivers/tty/serial/serial-tegra.c

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