clk: renesas: r8a77980: Correct parent clock of PCIEC0

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According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
December 22, 2017, the parent clock of the PCIe module clock on R-Car
V3H is S2D2.

Fixes: ce15783c51 ("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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Geert Uytterhoeven 2018-04-09 13:50:41 +02:00

parent 279ebbcae5

commit 246e232437

1 changed files with 1 additions and 1 deletions

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drivers/clk/renesas/r8a77980-cpg-mssr.c

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