clk: Support bypassing dividers

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When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU
code expects the mux to be applied first, the divider second.

On the JZ4760, and maybe on some other SoCs, some clocks also have a mux
setting and a divider, but the divider is not applied to all parents
selectable from the mux.

This could be solved by creating two clocks, one with CGU_CLK_DIV and
one with CGU_CLK_MUX, but that would increase the number of clocks.

Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit
corresponding to the parent clock's index is set, the divider is
bypassed.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

This commit is contained in:

Paul Cercueil 2021-05-30 17:49:19 +01:00 • committed by Stephen Boyd

parent 2e1ae04f7f

commit 249592bf6d

5 changed files with 42 additions and 29 deletions

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33

drivers/clk/ingenic/cgu.c

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2

drivers/clk/ingenic/cgu.h

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12

drivers/clk/ingenic/jz4725b-cgu.c

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12

drivers/clk/ingenic/jz4740-cgu.c

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12

drivers/clk/ingenic/jz4770-cgu.c

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