From 25a7255afb70b608672a50c921edf20d83ce745e Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 17 Sep 2026 15:33:39 -0700 Subject: [PATCH] drm/xe: Consolidate semaphore instruction definitions Drop the definition of MI_SEMAPHORE_WAIT_TOKEN and replace its uses with MI_SEMAPHORE_WAIT. Both #define's were representing the same opcode 0x1C and this GPU instruction has always been named "MI_SEMAPHORE_WAIT" in the official specs. The "*_TOKEN" definition appears to have been copied from i915's code. i915 needed two separate definitions to reflect the slightly different instruction lengths gen8-gen11 platforms (4 dwords) vs gen12 and later platforms (5 dwords, with the extra dword representing a token), but Xe only supports newer platforms with the 5-dword form, so only a single definition is needed and should match the official name given in the specs. Bspec: 14054, 45749, 60244 Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260917-semaphore_inst-v1-1-61e49405f71d@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 7 +------ drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++-- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h index ad7d98f2dbba..835ef75bbeb1 100644 --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h @@ -36,6 +36,7 @@ #define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) #define MI_SEMW_GGTT REG_BIT(22) +#define MI_SEMW_REGISTER_POLL REG_BIT(16) #define MI_SEMW_POLL REG_BIT(15) #define MI_SEMW_COMPARE_OP_MASK REG_GENMASK(14, 12) #define COMPARE_OP_SAD_GT_SDD 0 @@ -94,10 +95,4 @@ #define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0) #define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x) -#define MI_SEMAPHORE_WAIT_TOKEN (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */ -#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16) -#define MI_SEMAPHORE_POLL REG_BIT(15) -#define MI_SEMAPHORE_CMP_OP_MASK REG_GENMASK(14, 12) -#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4) - #endif diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index 08b4a4283e96..46ab1f0f3564 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -55,8 +55,8 @@ __emit_aux_table_inv(u32 *cmd, const struct xe_reg reg, u32 adj_offset) MI_LRI_MMIO_REMAP_EN; *cmd++ = reg.addr + adj_offset; *cmd++ = AUX_INV; - *cmd++ = MI_SEMAPHORE_WAIT_TOKEN | MI_SEMAPHORE_REGISTER_POLL | - MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_EQ_SDD; + *cmd++ = MI_SEMAPHORE_WAIT | MI_SEMW_REGISTER_POLL | + MI_SEMW_POLL | MI_SEMW_COMPARE(SAD_EQ_SDD); *cmd++ = 0; *cmd++ = reg.addr + adj_offset; *cmd++ = 0;