ASoC: amd: ps: add ZSC control register programming sequence

Browse source

Add ZSC Control register programming sequence for ACP D0 and D3 state
transitions for ACP6.3 platform. This will allow ACP to enter low power
state when ACP enters D3 state. When ACP enters D0 State, ZSC control
should be disabled.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20241203081940.3390281-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Vijendar Mukunda 2024-12-03 13:49:40 +05:30 • committed by Mark Brown

parent bcbf421d21

commit 25cd677636

No known key found for this signature in database

GPG key ID: 24D68B725D5487D0

1 changed files with 11 additions and 4 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

15

sound/soc/amd/ps/pci-ps.c

View file