ath9k_hw: always set the core clock for AR9271

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When initializing the PLL on AR9271 we always need
to set the core clock to 117MHz. While at it remove
the baud rate settings for the serial device on the
AR9271, the default settings work well unless you
want to customize it.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

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Sujith 2010-03-17 14:25:22 +05:30 • committed by John W. Linville

parent 02afa2a01b

commit 25e2ab17fd

1 changed files with 2 additions and 32 deletions

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drivers/net/wireless/ath/ath9k/hw.c

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