clk: vc5: Enable addition output configurations of the Versaclock

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The existing driver is expecting the Versaclock to be pre-programmed,
and only sets the output frequency.  Unfortunately, not all devices
are pre-programmed, and the Versaclock chip has more options beyond
just the frequency.

This patch enables the following additional features:

   - Programmable voltage: 1.8V, 2.5V, or 3.3V​
   - Slew Percentage of normal: 85%, 90%, or 100%
   - Output Type: LVPECL, CMOS, HCSL, or LVDS

Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200603154329.31579-3-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Adam Ford 2020-06-03 10:43:29 -05:00 • committed by Stephen Boyd

parent 34662f6e30

commit 260249f929

1 changed files with 156 additions and 0 deletions

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drivers/clk/clk-versaclock5.c

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