riscv: dts: microchip: convert clock and reset to use syscon

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The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt control
functionality. Re-write the devicetree to describe the sys explicitly,
as its own node, rather than as a region of the clock node.
Correspondingly, the phandles to the reset controller must be updated to
the new provider. The drivers will continue to support the old way of
doing things.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Conor Dooley 2025-11-10 11:23:52 +00:00

parent 6f86a41d21

commit 26535e8444

1 changed files with 12 additions and 7 deletions

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arch/riscv/boot/dts/microchip/mpfs.dtsi

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