drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih

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[ Upstream commit 8b22f04833 ]

Port this change to vega20_ih.c:
commit afbf7955ff ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts")

Original commit message:
"Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.

How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW."

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Victor Lu 2024-07-18 18:01:23 -04:00 • committed by Greg Kroah-Hartman

parent 166df51487

commit 266a3354f7

1 changed files with 27 additions and 0 deletions

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drivers/gpu/drm/amd/amdgpu/vega20_ih.c

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