clk: rockchip: allow varying mux parameters for cpuclk pll-sources

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Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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This commit is contained in:

Xing Zheng 2016-03-09 10:37:03 +08:00 • committed by Heiko Stuebner

parent 9387bfd19b

commit 268aebaa24

7 changed files with 45 additions and 11 deletions

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29

drivers/clk/rockchip/clk-cpu.c

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3

drivers/clk/rockchip/clk-rk3036.c

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6

drivers/clk/rockchip/clk-rk3188.c

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3

drivers/clk/rockchip/clk-rk3228.c

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3

drivers/clk/rockchip/clk-rk3288.c

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6

drivers/clk/rockchip/clk-rk3368.c

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6

drivers/clk/rockchip/clk.h

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