x86: HPET_MSI Initialise per-cpu HPET timers

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Initialize a per CPU HPET MSI timer when possible. We retain the HPET
timer 0 (IRQ 0) and timer 1 (IRQ 8) as is when legacy mode is being used. We
setup the remaining HPET timers as per CPU MSI based timers. This per CPU
timer will eliminate the need for timer broadcasting with IRQ 0 when there
is non-functional LAPIC timer across CPU deep C-states.

If there are more CPUs than number of available timers, CPUs that do not
find any timer to use will continue using LAPIC and IRQ 0 broadcast.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

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venkatesh.pallipadi@intel.com 2008-09-05 18:02:18 -07:00 • committed by Ingo Molnar

parent 4588c1f035

commit 26afe5f2fb

1 changed files with 293 additions and 2 deletions

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arch/x86/kernel/hpet.c

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