drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates

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In case of UHBR rates, we do not need to explicitly enable FEC by writing
to DP_TP_CTL register.
For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
setting fec_enable to false. However, it gets overwritten in
intel_dp_dsc_compute_config(). This change keeps fec_enable false across
MST and SST use-cases for UHBR rates.

While at it, add a comment explaining why we don't enable FEC in eDP v1.5.

v2: Correct logic to cater to SST use-cases (Jani)

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822061448.4085693-1-chaitanya.kumar.borah@intel.com

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Chaitanya Kumar Borah 2024-08-22 11:44:48 +05:30 • committed by Suraj Kandpal

parent 9c2338ac45

commit 26c85e7f40

1 changed files with 7 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_dp.c

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