drm/i915: Assert that VRR is off during vblank evasion if necessary

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Whenever we change the actual transcoder timings (clock via
seamless M/N, full modeset, (or soon) vtotal via LRR) we
want the timing generator to be in non-VRR during the commit.
Warn if we forgot to turn VRR off prior to vblank evasion.

Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901130440.2085-12-ville.syrjala@linux.intel.com
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

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Ville Syrjälä 2023-09-01 16:04:39 +03:00

parent 0ce013a4e8

commit 26f03ef816

1 changed files with 4 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_crtc.c

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