From 7c3bc1952dd2b02983c06632b2d342823e9d6b96 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 1 Sep 2023 15:32:32 +0200 Subject: [PATCH 01/48] arm64: dts: ti: verdin-am62: add iw416 based bluetooth Add NXP IW416 based u-blox MAYA-W1 Bluetooth (using btnxpuart) as used on the V1.1 SoMs. Wi-Fi is and was already using mwifiex. Signed-off-by: Marcel Ziswiler Link: https://lore.kernel.org/r/20230901133233.105546-1-marcel@ziswiler.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi index 90ddc71bcd30..a6808b10c7b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi @@ -35,5 +35,11 @@ &sdhci2 { &main_uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; }; From 87e437a0fb6cbecbabff293061793b32e3bcd3b1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 11:25:33 -0500 Subject: [PATCH 02/48] arm64: dts: ti: k3-am625: Add boot phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. On TI K3 AM625 SoC, only secure_proxy_sa3 and esm nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. Add bootph-all for all other nodes that are used in the bootloader on K3 AM625 SoC, and bootph-pre-ram is not needed specifically for any other node in kernel dts. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911162535.1044560-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 10 ++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 3 +++ 4 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 284b90c94da8..ac760d9b831d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -81,6 +81,7 @@ audio_refclk1: clock-controller@82e4 { }; dmss: bus@48000000 { + bootph-all; compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -90,6 +91,7 @@ dmss: bus@48000000 { ti,sci-dev-id = <25>; secure_proxy_main: mailbox@4d000000 { + bootph-all; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -165,6 +167,7 @@ main_pktdma: dma-controller@485c0000 { }; dmsc: system-controller@44043000 { + bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; @@ -174,16 +177,19 @@ dmsc: system-controller@44043000 { reg = <0x00 0x44043000 0x00 0xfe0>; k3_pds: power-controller { + bootph-all; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-all; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-all; compatible = "ti,sci-reset"; #reset-cells = <2>; }; @@ -202,6 +208,7 @@ crypto: crypto@40900000 { }; secure_proxy_sa3: mailbox@43600000 { + bootph-pre-ram; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -217,6 +224,7 @@ secure_proxy_sa3: mailbox@43600000 { }; main_pmx0: pinctrl@f4000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; #pinctrl-cells = <1>; @@ -225,12 +233,14 @@ main_pmx0: pinctrl@f4000 { }; main_esm: esm@420000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x420000 0x00 0x1000>; ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; }; main_timer0: timer@2400000 { + bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 80a3e1db26a9..0e0b234581c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -7,6 +7,7 @@ &cbass_mcu { mcu_pmx0: pinctrl@4084000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; #pinctrl-cells = <1>; @@ -15,6 +16,7 @@ mcu_pmx0: pinctrl@4084000 { }; mcu_esm: esm@4100000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x4100000 0x00 0x1000>; ti,esm-pins = <0>, <1>, <2>, <85>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index eae052887186..fef76f52a52e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -7,6 +7,7 @@ &cbass_wakeup { wkup_conf: syscon@43000000 { + bootph-all; compatible = "syscon", "simple-mfd"; reg = <0x00 0x43000000 0x00 0x20000>; #address-cells = <1>; @@ -14,6 +15,7 @@ wkup_conf: syscon@43000000 { ranges = <0x0 0x00 0x43000000 0x20000>; chipid: chipid@14 { + bootph-all; compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index 11f14eef2d44..f1e15206e1ce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -47,6 +47,7 @@ pmu: pmu { }; cbass_main: bus@f0000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -86,6 +87,7 @@ cbass_main: bus@f0000 { <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; cbass_mcu: bus@4000000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -93,6 +95,7 @@ cbass_mcu: bus@4000000 { }; cbass_wakeup: bus@b00000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 944adefc7f88aec1adf5f76f593d483938bc5e4e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 11:25:34 -0500 Subject: [PATCH 03/48] arm64: dts: ti: k3-am625-beagleplay: Add boot phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for beagleplay boot devices. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911162535.1044560-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 7cfdf562b53b..f646d1ec4c05 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -46,6 +46,7 @@ chosen { }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -83,6 +84,7 @@ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { }; vsys_5v0: regulator-1 { + bootph-all; compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; regulator-min-microvolt = <5000000>; @@ -93,6 +95,7 @@ vsys_5v0: regulator-1 { vdd_3v3: regulator-2 { /* output of TLV62595DMQR-U12 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; regulator-min-microvolt = <3300000>; @@ -118,6 +121,7 @@ wlan_en: regulator-3 { vdd_3v3_sd: regulator-4 { /* output of TPS22918DBVR-U21 */ + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&vdd_3v3_sd_pins_default>; @@ -132,6 +136,7 @@ vdd_3v3_sd: regulator-4 { }; vdd_sd_dv: regulator-5 { + bootph-all; compatible = "regulator-gpio"; regulator-name = "sd_hs200_switch"; pinctrl-names = "default"; @@ -146,9 +151,11 @@ vdd_sd_dv: regulator-5 { }; leds { + bootph-all; compatible = "gpio-leds"; led-0 { + bootph-all; gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; function = LED_FUNCTION_HEARTBEAT; @@ -156,6 +163,7 @@ led-0 { }; led-1 { + bootph-all; gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; function = LED_FUNCTION_DISK_ACTIVITY; @@ -163,16 +171,19 @@ led-1 { }; led-2 { + bootph-all; gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_CPU; }; led-3 { + bootph-all; gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_LAN; }; led-4 { + bootph-all; gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_WLAN; }; @@ -245,6 +256,7 @@ cpsw3g_phy1: ethernet-phy@1 { &main_pmx0 { gpio0_pins_default: gpio0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ @@ -264,6 +276,7 @@ AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ }; vdd_sd_dv_pins_default: vdd-sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; @@ -283,6 +296,7 @@ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ }; local_i2c_pins_default: local-i2c-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ @@ -321,6 +335,7 @@ AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ }; emmc_pins_default: emmc-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -336,12 +351,14 @@ AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ }; vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ >; }; sd_pins_default: sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -418,6 +435,7 @@ AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ }; mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ @@ -426,6 +444,7 @@ AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ }; console_pins_default: console-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ @@ -597,6 +616,7 @@ &cpsw3g_mdio { }; &main_gpio0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&gpio0_pins_default>; gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ @@ -616,6 +636,7 @@ &main_gpio0 { }; &main_gpio1 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&mikrobus_gpio_pins_default>; gpio-line-names = "", "", "", "", "", /* 0-4 */ @@ -633,6 +654,7 @@ &main_gpio1 { }; &main_i2c0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&local_i2c_pins_default>; clock-frequency = <400000>; @@ -651,6 +673,7 @@ rtc: rtc@68 { }; tps65219: pmic@30 { + bootph-all; compatible = "ti,tps65219"; reg = <0x30>; buck1-supply = <&vsys_5v0>; @@ -801,6 +824,7 @@ &main_spi2 { }; &sdhci0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; ti,driver-strength-ohm = <50>; @@ -810,6 +834,7 @@ &sdhci0 { &sdhci1 { /* SD/MMC */ + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&sd_pins_default>; @@ -850,6 +875,7 @@ wlcore: wlcore@2 { }; &main_uart0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&console_pins_default>; status = "okay"; From c412c2f26eed08b1836ccf79f5547b67c1b55d5d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 11:25:35 -0500 Subject: [PATCH 04/48] arm64: dts: ti: k3-am625-sk: Add boot phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for am625-sk boot devices. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911162535.1044560-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 27 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 16 +++++++++++ 2 files changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 7c98c1b855d1..b18092497c9a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -31,6 +31,7 @@ memory@80000000 { vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vmain_pd"; regulator-min-microvolt = <5000000>; @@ -41,6 +42,7 @@ vmain_pd: regulator-0 { vcc_5v0: regulator-1 { /* Output of LM34936 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vcc_5v0"; regulator-min-microvolt = <5000000>; @@ -52,6 +54,7 @@ vcc_5v0: regulator-1 { vcc_3v3_sys: regulator-2 { /* output of LM61460-Q1 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; regulator-min-microvolt = <3300000>; @@ -63,6 +66,7 @@ vcc_3v3_sys: regulator-2 { vdd_mmc1: regulator-3 { /* TPS22918DBVR */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; @@ -75,6 +79,7 @@ vdd_mmc1: regulator-3 { vdd_sd_dv: regulator-4 { /* Output of TLV71033 */ + bootph-all; compatible = "regulator-gpio"; regulator-name = "tlv71033"; pinctrl-names = "default"; @@ -102,6 +107,7 @@ vcc_1v8: regulator-5 { &main_pmx0 { main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -119,6 +125,7 @@ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ }; ospi0_pins_default: ospi0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -135,20 +142,32 @@ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; }; +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + &main_i2c1 { + bootph-all; exp1: gpio@22 { + bootph-all; compatible = "ti,tca6424"; reg = <0x22>; gpio-controller; @@ -207,12 +226,18 @@ mbox_m4_0: mbox-m4-0 { }; }; +&fss { + bootph-all; +}; + &ospi0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -225,6 +250,7 @@ flash@0 { cdns,read-delay = <4>; partitions { + bootph-all; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -260,6 +286,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-pre-ram; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 677ff8de4b6e..19f57ead4ebd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -28,6 +28,7 @@ chosen { }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -130,6 +131,7 @@ hdmi_connector_in: endpoint { &main_pmx0 { /* First pad number is ALW package and second is AMC package */ main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ @@ -137,6 +139,7 @@ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ }; main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ @@ -167,6 +170,7 @@ AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ }; main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ @@ -182,6 +186,7 @@ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ @@ -207,6 +212,7 @@ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ }; main_rgmii1_pins_default: main-rgmii1-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ @@ -274,6 +280,7 @@ AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ @@ -285,12 +292,14 @@ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ + bootph-pre-ram; status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -298,6 +307,7 @@ &main_uart0 { &main_uart1 { /* Main UART1 is used by TIFS firmware */ + bootph-pre-ram; status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; @@ -390,6 +400,7 @@ sii9022_out: endpoint { }; &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; @@ -399,6 +410,7 @@ &sdhci0 { &sdhci1 { /* SD/MMC */ + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; @@ -407,21 +419,25 @@ &sdhci1 { }; &cpsw3g { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; }; &cpsw_port1 { + bootph-all; phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; }; &cpsw3g_mdio { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; cpsw3g_phy0: ethernet-phy@0 { + bootph-all; reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; From 8d5bfa637f0f04a71166b9bde0ef022b08986296 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 12:29:00 -0500 Subject: [PATCH 05/48] arm64: dts: ti: k3-am64: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. On TI K3 AM642 SoC, only esm nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. Add bootph-all for all other nodes that are used in the bootloader on K3 AM642 SoC, and bootph-pre-ram is not needed specifically for any other node in kernel dts. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911172902.1057417-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 ++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 0df54a741824..1933c9dd1d9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -38,6 +38,7 @@ sproxy-sram@1fc000 { }; main_conf: syscon@43000000 { + bootph-all; compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x0 0x43000000 0x0 0x20000>; #address-cells = <1>; @@ -45,6 +46,7 @@ main_conf: syscon@43000000 { ranges = <0x0 0x0 0x43000000 0x20000>; chipid@14 { + bootph-all; compatible = "ti,am654-chipid"; reg = <0x00000014 0x4>; }; @@ -96,6 +98,7 @@ gic_its: msi-controller@1820000 { }; dmss: bus@48000000 { + bootph-all; compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -105,6 +108,7 @@ dmss: bus@48000000 { ti,sci-dev-id = <25>; secure_proxy_main: mailbox@4d000000 { + bootph-all; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -188,6 +192,7 @@ main_pktdma: dma-controller@485c0000 { }; dmsc: system-controller@44043000 { + bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; @@ -197,22 +202,26 @@ dmsc: system-controller@44043000 { reg = <0x00 0x44043000 0x00 0xfe0>; k3_pds: power-controller { + bootph-all; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-all; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-all; compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; main_pmx0: pinctrl@f4000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2d0>; #pinctrl-cells = <1>; @@ -221,6 +230,7 @@ main_pmx0: pinctrl@f4000 { }; main_timer0: timer@2400000 { + bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; interrupts = ; @@ -365,6 +375,7 @@ main_timer11: timer@24b0000 { }; main_esm: esm@420000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x420000 0x00 0x1000>; ti,esm-pins = <160>, <161>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 686d49790721..b9508072bebb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -146,6 +146,7 @@ mcu_gpio0: gpio@4201000 { }; mcu_pmx0: pinctrl@4084000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0x4084000 0x00 0x84>; #pinctrl-cells = <1>; @@ -154,6 +155,7 @@ mcu_pmx0: pinctrl@4084000 { }; mcu_esm: esm@4100000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x4100000 0x00 0x1000>; ti,esm-pins = <0>, <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 8e9c2bc70f4d..0187c42aed4f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -47,6 +47,7 @@ pmu: pmu { }; cbass_main: bus@f4000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -85,6 +86,7 @@ cbass_main: bus@f4000 { <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; cbass_mcu: bus@4000000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 33830e077797ce4d7317b83a145f03bfde06ad4c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 12:29:01 -0500 Subject: [PATCH 06/48] arm64: dts: ti: k3-am642-evm: Add boot phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for AM642-evm boot devices. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911172902.1057417-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index b4a1f73d4fb1..d0e1191baecd 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -35,6 +35,7 @@ aliases { }; memory@80000000 { + bootph-all; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -108,6 +109,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { evm_12v0: regulator-0 { /* main DC jack */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "evm_12v0"; regulator-min-microvolt = <12000000>; @@ -129,6 +131,7 @@ vsys_5v0: regulator-1 { vsys_3v3: regulator-2 { /* output of LM5140 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; @@ -140,6 +143,7 @@ vsys_3v3: regulator-2 { vdd_mmc1: regulator-3 { /* TPS2051BD */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; @@ -161,6 +165,7 @@ vddb: regulator-4 { }; vtt_supply: regulator-5 { + bootph-all; compatible = "regulator-fixed"; regulator-name = "vtt"; pinctrl-names = "default"; @@ -251,6 +256,7 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ }; main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -269,6 +275,7 @@ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ }; main_i2c0_pins_default: main-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ @@ -276,6 +283,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ }; main_i2c1_pins_default: main-i2c1-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ @@ -283,6 +291,7 @@ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ }; mdio1_pins_default: mdio1-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ @@ -290,6 +299,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ }; rgmii1_pins_default: rgmii1-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ @@ -307,6 +317,7 @@ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ }; rgmii2_pins_default: rgmii2-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -324,6 +335,7 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ }; main_usb0_pins_default: main-usb0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; @@ -366,6 +378,7 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ }; ddr_vtt_pins_default: ddr-vtt-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; @@ -373,6 +386,7 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ }; &main_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -387,6 +401,7 @@ &main_uart1 { }; &main_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -400,12 +415,14 @@ eeprom@50 { }; &main_i2c1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; exp1: gpio@22 { + bootph-all; compatible = "ti,tca6424"; reg = <0x22>; gpio-controller; @@ -438,6 +455,10 @@ display@3c { }; }; +&main_gpio0 { + bootph-all; +}; + /* mcu_gpio0 is reserved for mcu firmware usage */ &mcu_gpio0 { status = "reserved"; @@ -467,6 +488,7 @@ &sdhci0 { &sdhci1 { /* SD/MMC */ + bootph-all; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; bus-width = <4>; @@ -476,11 +498,13 @@ &sdhci1 { }; &usbss0 { + bootph-all; ti,vbus-divider; ti,usb2-only; }; &usb0 { + bootph-all; dr_mode = "otg"; maximum-speed = "high-speed"; pinctrl-names = "default"; @@ -488,11 +512,13 @@ &usb0 { }; &cpsw3g { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { + bootph-all; phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; }; @@ -503,11 +529,13 @@ &cpsw_port2 { }; &cpsw3g_mdio { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default>; cpsw3g_phy0: ethernet-phy@0 { + bootph-all; reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; From 4669288219a7f77c6ff992d10ce6a20660863979 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 11 Sep 2023 12:29:02 -0500 Subject: [PATCH 07/48] arm64: dts: ti: k3-am642-sk: Add boot phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for AM642-sk boot devices. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230911172902.1057417-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 722fd285a34e..f29c8a9b59ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -34,6 +34,7 @@ aliases { }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -107,6 +108,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { vusb_main: regulator-0 { /* USB MAIN INPUT 5V DC */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vusb_main5v0"; regulator-min-microvolt = <5000000>; @@ -117,6 +119,7 @@ vusb_main: regulator-0 { vcc_3v3_sys: regulator-1 { /* output of LP8733xx */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; regulator-min-microvolt = <3300000>; @@ -128,6 +131,7 @@ vcc_3v3_sys: regulator-1 { vdd_mmc1: regulator-2 { /* TPS2051BD */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; @@ -234,6 +238,7 @@ led-7 { &main_pmx0 { main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ @@ -248,6 +253,7 @@ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ }; main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -257,6 +263,7 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ }; main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -266,12 +273,14 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ }; main_usb0_pins_default: main-usb0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; main_i2c0_pins_default: main-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ @@ -279,6 +288,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ }; main_i2c1_pins_default: main-i2c1-default-pins { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ @@ -367,6 +377,7 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ }; &main_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -375,12 +386,14 @@ &main_uart0 { &main_uart1 { /* main_uart1 is reserved for firmware usage */ + bootph-pre-ram; status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -393,12 +406,14 @@ eeprom@51 { }; &main_i2c1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; exp1: gpio@70 { + bootph-all; compatible = "nxp,pca9538"; reg = <0x70>; gpio-controller; @@ -445,6 +460,7 @@ wlcore: wlcore@2 { &sdhci1 { /* SD/MMC */ + bootph-all; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; bus-width = <4>; @@ -454,11 +470,22 @@ &sdhci1 { }; &serdes_ln_ctrl { + bootph-all; idle-states = ; }; +&serdes_refclk { + bootph-all; +}; + +&serdes_wiz0 { + bootph-all; +}; + &serdes0 { + bootph-all; serdes0_usb_link: phy@0 { + bootph-all; reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -468,10 +495,12 @@ serdes0_usb_link: phy@0 { }; &usbss0 { + bootph-all; ti,vbus-divider; }; &usb0 { + bootph-all; dr_mode = "host"; maximum-speed = "super-speed"; pinctrl-names = "default"; From 35be6ac964450687ab39b846d65ee1cb2a352280 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 12 Sep 2023 10:03:08 +0530 Subject: [PATCH 08/48] arm64: dts: ti: k3-j721s2-evm-gesi: Specify base dtb for overlay file Specify the base dtb file k3-j721s2-common-proc-board.dtb on which the k3-j721s2-evm-gesi-exp-board.dtbo overlay has to be applied. Name the resulting dtb as k3-j721s2-evm.dtb. Fixes: cac04e27f093 ("arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI") Reported-by: Rob Herring Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20230912043308.20629-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index e7b8e2e7f083..51dab9499cd0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -66,6 +66,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo +k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb From dc16ab3ebf9d2b322f7463c5112f8875dcaca0e5 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Tue, 12 Sep 2023 15:30:36 +0200 Subject: [PATCH 09/48] arm64: dts: ti: k3-am64: Fix indentation in watchdog nodes Use single instead of double tab. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20230912133036.257277-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 1933c9dd1d9f..2e50030d09ad 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1169,21 +1169,21 @@ ecap2: pwm@23120000 { }; main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; }; main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0xe010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; }; icssg0: icssg@30000000 { From a1cd710f56c145bc7e7fc2bfbe332d944d5338cd Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 14 Sep 2023 11:30:27 +0200 Subject: [PATCH 10/48] arm64: dts: ti: phycore-am64: Add RTC interrupt pin Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device tree if available") we can now use the interrupt pin of the RTC. Let's add interrupt pin definitions to the SoM RTC. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20230914093027.3901602-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 1c2c8f0daca9..f87f09d83c95 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -126,6 +126,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; }; + + rtc_pins_default: rtc-defaults-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */ + >; + }; }; &cpsw3g { @@ -177,6 +183,11 @@ eeprom@50 { i2c_som_rtc: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <70 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; From 2f40c6df3dcc1341afd99cd1a4de035f807c8a03 Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 20 Sep 2023 11:08:34 +0530 Subject: [PATCH 11/48] arm64: dts: ti: k3-am654-base-board: Add I2C I/O expander AM654 baseboard has two TCA9554 I/O expander on the WKUP_I2C0 bus. The expander at address 0x38 is used to detect daughter cards. Add a node for this I/O expander. Signed-off-by: Ravi Gunasekaran Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230920053834.21399-1-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index f5c26e9fba98..1637ec5ab5ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -369,6 +369,13 @@ vdd_mpu: regulator@60 { ti,enable-vout-discharge; }; + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + }; + pca9554: gpio@39 { compatible = "nxp,pca9554"; reg = <0x39>; From 664e2852aa9142193c2e241327631f032b966742 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Fri, 22 Sep 2023 14:30:03 +0200 Subject: [PATCH 12/48] arm64: dts: ti: verdin-am62: disable MIPI DSI bridge Keep the DPI to MIPI-DSI bridge disabled in the SoM dtsi file. The display chain is not wholly described in the device tree file, on Verdin product family the displays are additional accessories that are configured/enabled using DT overlays. With this enabled we have issues when a display is enabled on TIDSS port1 (LVDS) and port0 (DSI) is not used. Fixes: 9e77200356ba ("arm64: dts: ti: verdin-am62: Add DSI display support") Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230922123003.25002-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 40992e7e4c30..5db52f237253 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1061,6 +1061,7 @@ dsi_bridge: dsi@e { vddc-supply = <®_1v2_dsi>; vddmipi-supply = <®_1v2_dsi>; vddio-supply = <®_1v8_dsi>; + status = "disabled"; dsi_bridge_ports: ports { #address-cells = <1>; From a716abbaa145d30653cee2f2644f9bd721117150 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Sat, 23 Sep 2023 11:00:46 +0300 Subject: [PATCH 13/48] arm64: dts: ti: k3-am64: Add GPIO expander on I2C0 A TCA9554 GPIO expander is present on I2C0. Add it. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20230923080046.5373-3-rogerq@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index d0e1191baecd..4dba18941015 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -407,6 +407,15 @@ &main_i2c0 { pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + gpio@38 { + /* TCA9554 */ + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HSE_DETECT"; + }; + eeprom@50 { /* AT24CM01 */ compatible = "atmel,24c1024"; From 33269ac0b768b07da017df173d52952625c57870 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Mon, 25 Sep 2023 17:14:44 +0200 Subject: [PATCH 14/48] arm64: dts: ti: k3-am625-beagleplay: Fix typo in ramoops reg Seems like the address value of the reg property was mistyped. Update reg to 0x9ca00000 to match node's definition. Fixes: f5a731f0787f ("arm64: dts: ti: Add k3-am625-beagleplay") Signed-off-by: Wadim Egorov Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230925151444.1856852-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index f646d1ec4c05..00891a0f8fc3 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -59,7 +59,7 @@ reserved-memory { ramoops: ramoops@9ca00000 { compatible = "ramoops"; - reg = <0x00 0x9c700000 0x00 0x00100000>; + reg = <0x00 0x9ca00000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; From 0997638a7580fc53e2162a480c8be521196f1319 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 26 Sep 2023 19:58:10 +0530 Subject: [PATCH 15/48] arm64: dts: ti: k3-j721e-mcu-wakeup: Add MCU domain ESM instance Currently J721E defines only the main_esm in DTS. Add node for mcu_esm as well. According to J721E TRM (12.11.2.2 ESM Environment) [1], we see that the interrupt line from ESMi (main_esm) is routed to MCU_ESM (mcu_esm). This is MCU_ESM0_LVL_IN_95 with interrupt ID 95. Configure mcu_esm accordingly so that errors from main_esm are routed to mcu_esm and handled. [1] https://www.ti.com/lit/zip/spruil1 Signed-off-by: Neha Malcom Francis Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230926142810.602384-1-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 05d6ef127ba7..fa8af20c7818 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -671,4 +671,11 @@ wkup_vtm0: temperature-sensor@42040000 { power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; From 1b70e86cb8506f358437ce9dccab8b9746c61e5d Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:09 +0530 Subject: [PATCH 16/48] arm64: dts: ti: k3-j721s2-mcu: Add MCU R5F cluster nodes The J721S2 SoCs have a dual-core Arm Cortex-R5F processor (R5FSS) subsystems/cluster in MCU voltage domain. It can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory, but otherwise are functionally similar to those on J721E SoCs. Add the DT nodes for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to each of the R5F cluster nodes. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MCU R5FSS0 Core0: j721s2-mcu-r5f0_0-fw (both in LockStep and Split mode) MCU R5FSS0 Core1: j721s2-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20231001181417.743306-2-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 2ddad9318554..56504578c464 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -655,4 +655,44 @@ wkup_vtm0: temperature-sensor@42040000 { power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <284>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 284 1>; + firmware-name = "j721s2-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <285>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 285 1>; + firmware-name = "j721s2-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; From 9a7b145b0ecdc7db7f06eb7edb1c2ed5e8f9a3b7 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:10 +0530 Subject: [PATCH 17/48] arm64: dts: ti: k3-j721s2-main: Add MAIN R5F remote processsor nodes The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters in MAIN voltage domain. Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory, but otherwise are functionally similar to those on J721E SoCs. Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two R5F cores are added as child nodes to each of the R5F cluster nodes. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split mode) MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split mode) MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20231001181417.743306-3-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 084f8f5b6699..cf439b96284d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1695,4 +1695,84 @@ dss: dss@4a00000 { dss_ports: ports { }; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <279>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 279 1>; + firmware-name = "j721s2-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <280>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 280 1>; + firmware-name = "j721s2-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 281 1>; + firmware-name = "j721s2-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <282>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 282 1>; + firmware-name = "j721s2-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; From fad9312e432db993ea47947db53dde85462967c1 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:11 +0530 Subject: [PATCH 18/48] arm64: dts: ti: k3-j721s2-main: Add C7x remote processsor nodes The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The C71x DSPs are 64 bit machine with fixed and floating point DSP operations. Similar to the R5F remote cores, the inter-processor communication between the main A72 cores and these DSP cores is achieved through shared memory and Mailboxes. The following firmware names are used by default for these DSP cores, and can be overridden in a board dts file if desired: MAIN C71_0 : j721s2-c71_0-fw MAIN C71_1 : j721s2-c71_1-fw Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20231001181417.743306-4-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index cf439b96284d..6d32544c8881 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1775,4 +1775,30 @@ main_r5fss1_core1: r5f@5f00000 { ti,loczrama = <1>; }; }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <8>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 8 1>; + firmware-name = "j721s2-c71_0-fw"; + status = "disabled"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <11>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 11 1>; + firmware-name = "j721s2-c71_1-fw"; + status = "disabled"; + }; }; From 3328b0419815bcc0c6d93c66f9c11eefca42a59b Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:12 +0530 Subject: [PATCH 19/48] arm64: dts: ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F Two carveout reserved memory nodes each have been added for each of the R5F remote processor device within both the MCU and MAIN domains for the TI J721S2 EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20231001181417.743306-5-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 156 +++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index a4006f328027..970340ff2c0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -29,6 +29,84 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; mux0: mux-controller { @@ -151,3 +229,81 @@ flash@0 { cdns,read-delay = <4>; }; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; From 35fa951c89f6abcb74f73643940b2656c0921353 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:13 +0530 Subject: [PATCH 20/48] arm64: dts: ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for C71x DSPs Two carveout reserved memory nodes each have been added for each of the C71x DSP for the TI J721S2 EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor supports a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20231001181417.743306-6-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 970340ff2c0a..dcad372620b1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -102,6 +102,30 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 { no-map; }; + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; @@ -272,6 +296,20 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, @@ -307,3 +345,17 @@ &main_r5fss1_core1 { memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; From 641d62f2012d99a7dc739bb1bd5718e149fd80ed Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:14 +0530 Subject: [PATCH 21/48] arm64: dts: ti: k3-am68-sk-som: Add DDR carveout memory nodes for R5F Two carveout reserved memory nodes each have been added for each of the R5F remote processor device within both the MCU and MAIN domains for the TI K3 AM68 SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Sinthu Raja Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231001181417.743306-7-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 156 +++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 6c9139f73201..beab405274ab 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -25,6 +25,84 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; }; @@ -49,3 +127,81 @@ eeprom@51 { reg = <0x51>; }; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; From 89e788b71b96f07be99b21107167c4f185b96405 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:15 +0530 Subject: [PATCH 22/48] arm64: dts: ti: k3-am68-sk-som: Add DDR carveout memory nodes for C71x DSP Two carveout reserved memory nodes each have been added for each of the C71x DSP for the TI K3 AM68 SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor supports a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Sinthu Raja Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231001181417.743306-8-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index beab405274ab..20861a0a46b0 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -98,6 +98,30 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 { no-map; }; + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; @@ -170,6 +194,20 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, @@ -205,3 +243,17 @@ &main_r5fss1_core1 { memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; From 567f75ab67d0d1b5ef4a2ca9d28f23e0876e1d61 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:16 +0530 Subject: [PATCH 23/48] arm64: dts: ti: k3-am69-sk: Add DDR carveout memory nodes for R5F Two carveout reserved memory nodes each have been added for each of the R5F remote processor device within both the MCU and MAIN domains for the TI K3 AM69 SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Sinthu Raja Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231001181417.743306-9-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 200 ++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 06993709111e..3cde9c644613 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -47,6 +47,102 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; }; vusb_main: regulator-vusb-main5v0 { @@ -248,6 +344,62 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ }; }; +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + &wkup_uart0 { /* Firmware usage */ status = "reserved"; @@ -362,3 +514,51 @@ &mcu_cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; From c2e7258dbd451fff84fac2375aaec2f56f57f0b3 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Sun, 1 Oct 2023 23:44:17 +0530 Subject: [PATCH 24/48] arm64: dts: ti: k3-am69-sk: Add DDR carveout memory nodes for C71x DSP Two carveout reserved memory nodes each have been added for each of the C71x DSP for the TI K3 AM69 SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor supports a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Sinthu Raja Signed-off-by: Apurva Nandan Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231001181417.743306-10-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 104 ++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 3cde9c644613..bc1d21ff6d03 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -143,6 +143,54 @@ main_r5fss2_core1_memory_region: r5f-memory@a7100000 { reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; }; vusb_main: regulator-vusb-main5v0 { @@ -400,6 +448,34 @@ mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { }; }; +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + &wkup_uart0 { /* Firmware usage */ status = "reserved"; @@ -562,3 +638,31 @@ &main_r5fss2_core1 { memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; }; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; From b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Thu, 21 Sep 2023 15:30:37 +0530 Subject: [PATCH 25/48] arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C lane swap. Update the macro definition for it. Signed-off-by: Sinthu Raja Signed-off-by: Ravi Gunasekaran Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230921100039.19897-2-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-serdes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index 29167f85c1f6..21b4886c47ba 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -111,7 +111,7 @@ #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_USB_SWAP 0x2 #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 From 73e8ec1b2d101fb030f6906c9d2799bea80e3804 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Thu, 21 Sep 2023 15:30:38 +0530 Subject: [PATCH 26/48] arm64: dts: ti: k3-am68-sk: Add DT node for PCIe AM68 Starter kit features with one PCIe M.2 Key M connector interfaced via two SerDes lanes. Update the SerDes configuration for PCIe. Signed-off-by: Sinthu Raja Signed-off-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20230921100039.19897-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 5df5946687b3..81c2307c77f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -553,3 +553,32 @@ dpi_out0: endpoint { }; }; }; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; From 067878e6cd25e071106eb7998165dd3cb46ff2ce Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Thu, 21 Sep 2023 15:30:39 +0530 Subject: [PATCH 27/48] arm64: dts: ti: k3-am68-sk: Add DT node for USB AM68 Starter kit has a USB3 hub that connects to the SerDes0 Lane 2. Update the SerDes configuration to support USB3. Signed-off-by: Sinthu Raja Signed-off-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20230921100039.19897-4-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 81c2307c77f9..1e1a82f9d2b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -573,6 +573,15 @@ serdes0_pcie_link: phy@0 { cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; }; + + serdes0_usb_link: phy@2 { + status = "okay"; + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; }; &pcie1_rc { @@ -582,3 +591,21 @@ &pcie1_rc { phy-names = "pcie-phy"; num-lanes = <2>; }; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 2 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; From 8e4e717be847913517977d9689ab88f1b86d71d8 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 28 Sep 2023 13:45:10 +0200 Subject: [PATCH 28/48] arm64: dts: ti: k3-am64-tqma64xxl: add supply regulator for I2C devices Describes the hardware better, and avoids a few warnings during boot: lm75 0-004a: supply vs not found, using dummy regulator at24 0-0050: supply vcc not found, using dummy regulator at24 0-0054: supply vcc not found, using dummy regulator Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/d5991041263c96c798b94c0844a1550e28daa3b1.1695901360.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 6229849b5d96..d82d4a98306a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -85,6 +85,15 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { no-map; }; }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; }; &main_i2c0 { @@ -96,11 +105,13 @@ &main_i2c0 { tmp1075: temperature-sensor@4a { compatible = "ti,tmp1075"; reg = <0x4a>; + vs-supply = <®_1v8>; }; eeprom0: eeprom@50 { compatible = "st,24c02", "atmel,24c02"; reg = <0x50>; + vcc-supply = <®_1v8>; pagesize = <16>; read-only; }; @@ -114,6 +125,7 @@ pcf85063: rtc@51 { eeprom1: eeprom@54 { compatible = "st,24c64", "atmel,24c64"; reg = <0x54>; + vcc-supply = <®_1v8>; pagesize = <32>; }; }; From ec30a50c72bdaa6007c999846675241b44b233d0 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 28 Sep 2023 13:45:11 +0200 Subject: [PATCH 29/48] arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add muxing for GPIOs on pin headers The pin headers X41 and X42 do not have a fixed function. All of these pins can be assigned to PRG0, but as a default, it makes more sense to configure them as simple GPIOs, as the MBaX4XxL is a starterkit/evaluation mainboard. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/77c30081154774ce31fc4306474a3afa52b07753.1695901360.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 76 ++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 04c15b64f0b7..7c49d30587d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -170,7 +170,8 @@ &main_gpio0 { &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_hog_pins>; + pinctrl-0 = <&main_gpio1_hog_pins>, + <&main_gpio1_pru_pins>; gpio-line-names = "", "", "", "", /* 0-3 */ "", "", "", "", /* 4-7 */ @@ -545,6 +546,79 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) >; }; + main_gpio1_pru_pins: main-gpio1-pru-pins { + pinctrl-single,pins = < + /* (Y1) PRG0_PRU0_GPO0.GPIO1_0 */ + AM64X_IOPAD(0x0160, PIN_INPUT, 7) + /* (R4) PRG0_PRU0_GPO1.GPIO1_1 */ + AM64X_IOPAD(0x0164, PIN_INPUT, 7) + /* (U2) PRG0_PRU0_GPO2.GPIO1_2 */ + AM64X_IOPAD(0x0168, PIN_INPUT, 7) + /* (V2) PRG0_PRU0_GPO3.GPIO1_3 */ + AM64X_IOPAD(0x016c, PIN_INPUT, 7) + /* (AA2) PRG0_PRU0_GPO4.GPIO1_4 */ + AM64X_IOPAD(0x0170, PIN_INPUT, 7) + /* (R3) PRG0_PRU0_GPO5.GPIO1_5 */ + AM64X_IOPAD(0x0174, PIN_INPUT, 7) + /* (T3) PRG0_PRU0_GPO6.GPIO1_6 */ + AM64X_IOPAD(0x0178, PIN_INPUT, 7) + /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ + AM64X_IOPAD(0x017c, PIN_INPUT, 7) + /* (T2) PRG0_PRU0_GPO8.GPIO1_8 */ + AM64X_IOPAD(0x0180, PIN_INPUT, 7) + /* (Y3) PRG0_PRU0_GPO11.GPIO1_11 */ + AM64X_IOPAD(0x018c, PIN_INPUT, 7) + /* (AA3) PRG0_PRU0_GPO12.GPIO1_12 */ + AM64X_IOPAD(0x0190, PIN_INPUT, 7) + /* (R6) PRG0_PRU0_GPO13.GPIO1_13 */ + AM64X_IOPAD(0x0194, PIN_INPUT, 7) + /* (V4) PRG0_PRU0_GPO14.GPIO1_14 */ + AM64X_IOPAD(0x0198, PIN_INPUT, 7) + /* (T5) PRG0_PRU0_GPO15.GPIO1_15 */ + AM64X_IOPAD(0x019c, PIN_INPUT, 7) + /* (U4) PRG0_PRU0_GPO16.GPIO1_16 */ + AM64X_IOPAD(0x01a0, PIN_INPUT, 7) + /* (U1) PRG0_PRU0_GPO17.GPIO1_17 */ + AM64X_IOPAD(0x01a4, PIN_INPUT, 7) + /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ + AM64X_IOPAD(0x01a8, PIN_INPUT, 7) + /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ + AM64X_IOPAD(0x01ac, PIN_INPUT, 7) + /* (Y2) PRG0_PRU1_GPO0.GPIO1_20 */ + AM64X_IOPAD(0x01b0, PIN_INPUT, 7) + /* (W2) PRG0_PRU1_GPO1.GPIO1_21 */ + AM64X_IOPAD(0x01b4, PIN_INPUT, 7) + /* (V3) PRG0_PRU1_GPO2.GPIO1_22 */ + AM64X_IOPAD(0x01b8, PIN_INPUT, 7) + /* (T4) PRG0_PRU1_GPO3.GPIO1_23 */ + AM64X_IOPAD(0x01bc, PIN_INPUT, 7) + /* (W3) PRG0_PRU1_GPO4.GPIO1_24 */ + AM64X_IOPAD(0x01c0, PIN_INPUT, 7) + /* (P4) PRG0_PRU1_GPO5.GPIO1_25 */ + AM64X_IOPAD(0x01c4, PIN_INPUT, 7) + /* (R5) PRG0_PRU1_GPO6.GPIO1_26 */ + AM64X_IOPAD(0x01c8, PIN_INPUT, 7) + /* (R1) PRG0_PRU1_GPO8.GPIO1_28 */ + AM64X_IOPAD(0x01d0, PIN_INPUT, 7) + /* (W4) PRG0_PRU1_GPO11.GPIO1_31 */ + AM64X_IOPAD(0x01dc, PIN_INPUT, 7) + /* (Y4) PRG0_PRU1_GPO12.GPIO1_32 */ + AM64X_IOPAD(0x01e0, PIN_INPUT, 7) + /* (T6) PRG0_PRU1_GPO13.GPIO1_33 */ + AM64X_IOPAD(0x01e4, PIN_INPUT, 7) + /* (U6) PRG0_PRU1_GPO14.GPIO1_34 */ + AM64X_IOPAD(0x01e8, PIN_INPUT, 7) + /* (U5) PRG0_PRU1_GPO15.GPIO1_35 */ + AM64X_IOPAD(0x01ec, PIN_INPUT, 7) + /* (AA4) PRG0_PRU1_GPO16.GPIO1_36 */ + AM64X_IOPAD(0x01f0, PIN_INPUT, 7) + /* (P2) PRG0_MDIO0_MDIO.GPIO1_40 */ + AM64X_IOPAD(0x0200, PIN_INPUT, 7) + /* (P3) PRG0_MDIO0_MDC.GPIO1_41 */ + AM64X_IOPAD(0x0204, PIN_INPUT, 7) + >; + }; + main_mcan0_pins: main-mcan0-pins { pinctrl-single,pins = < /* (B17) MCAN0_RX */ From 92039884c9b57d14601c6e0e913b184dd2bff75c Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 28 Sep 2023 13:45:12 +0200 Subject: [PATCH 30/48] arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add chassis-type Set the "embedded" chassis-type for the MBaX4XxL. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/55bf14afa377b9bbc1d6c4647895c51c018ae761.1695901360.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 7c49d30587d2..1cb44fb9d272 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -19,6 +19,7 @@ / { compatible = "tq,am642-tqma6442l-mbax4xxl", "tq,am642-tqma6442l", "ti,am642"; model = "TQ-Systems TQMa64xxL SoM on MBax4xxL carrier board"; + chassis-type = "embedded"; aliases { ethernet0 = &cpsw_port1; From 06a0d54202e0de04e62c1991d39d6c7595f0d88a Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 28 Sep 2023 13:45:13 +0200 Subject: [PATCH 31/48] arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: update gpio-led configuration Replace the deprecated label property with color/function. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/79cb3cdfed19962ce0d4ae558de897695658a81f.1695901360.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 1cb44fb9d272..d95d80076a42 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -59,12 +60,14 @@ gpio-leds { pinctrl-0 = <&mcu_gpio_leds_pins>; led-0 { - label = "led0"; gpios = <&mcu_gpio0 8 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; }; led-1 { - label = "led1"; gpios = <&mcu_gpio0 9 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; }; }; From 1d181c96ef3b6f9b29474fb18eb9f426bb6b16ac Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 3 Oct 2023 14:41:30 +0530 Subject: [PATCH 32/48] arm64: dts: ti: k3-am62a-main: Add nodes for McASP Same as AM62, AM62A has three instances of McASP which can be used for transmitting or receiving digital audio in various formats. Reviewed-by: Jayesh Choudhary Reviewed-by: Devarsh Thakkar Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20231003-mcasp_am62a-v3-1-2b631ff319ca@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 3198af08fb9f..4ae7fdc5221b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -816,4 +816,64 @@ ecap2: pwm@23120000 { clock-names = "fck"; status = "disabled"; }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; }; From 770480e7eb729d49f2a10530d628e9778c1b3bd8 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 3 Oct 2023 14:41:31 +0530 Subject: [PATCH 33/48] arm64: dts: ti: k3-am62a7-sk: Split vcc_3v3 regulators VCC_3V3_MAIN is the output of LM5141-Q1, and it serves as an input to TPS22965DSGT which produces VCC_3V3_SYS. [1] Link: https://www.ti.com/lit/zip/sprr459 [1] Signed-off-by: Jai Luthra Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20231003-mcasp_am62a-v3-2-2b631ff319ca@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index cff283c75f8e..c689d3da2def 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -79,10 +79,10 @@ vcc_5v0: regulator-1 { regulator-boot-on; }; - vcc_3v3_sys: regulator-2 { + vcc_3v3_main: regulator-2 { /* output of LM5141-Q1 */ compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; + regulator-name = "vcc_3v3_main"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vmain_pd>; @@ -101,6 +101,17 @@ vdd_mmc1: regulator-3 { gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + vcc_3v3_sys: regulator-4 { + /* output of TPS222965DSGT */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; From 63e5aa69b821472a3203a29e17c025329c1b151f Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 3 Oct 2023 14:41:32 +0530 Subject: [PATCH 34/48] arm64: dts: ti: k3-am62a7-sk: Drop i2c-1 to 100Khz The TLV320AIC3106 audio codec is interfaced on the i2c-1 bus. With the default rate of 400Khz the i2c register writes fail to sync: [ 36.026387] tlv320aic3x 1-001b: Unable to sync registers 0x16-0x16. -110 [ 38.101130] omap_i2c 20010000.i2c: controller timed out Dropping the rate to 100Khz fixes the issue. Fixes: 38c4a08c820c ("arm64: dts: ti: Add support for AM62A7-SK") Reviewed-by: Devarsh Thakkar Reviewed-by: Aradhya Bhatia Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20231003-mcasp_am62a-v3-3-2b631ff319ca@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index c689d3da2def..866b2725f775 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -261,7 +261,7 @@ &main_i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; exp1: gpio@22 { compatible = "ti,tca6424"; From 3a8222080334fd0ffec9a6a563304f77571a1853 Mon Sep 17 00:00:00 2001 From: Julien Panis Date: Tue, 3 Oct 2023 14:41:33 +0530 Subject: [PATCH 35/48] arm64: dts: ti: k3-am62a7-sk: Add support for TPS6593 PMIC This patch adds support for TPS6593 PMIC on main I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Julien Panis Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20231003-mcasp_am62a-v3-4-2b631ff319ca@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 866b2725f775..377ab823bbcc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -232,6 +232,20 @@ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ }; }; +&mcu_pmx0 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -255,6 +269,87 @@ usb_con_hs: endpoint { }; }; }; + + tps659312: pmic@48 { + compatible = "ti,tps6593-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + buck5-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&buck5>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name = "vcc_core"; + regulator-min-microvolt = <715000>; + regulator-max-microvolt = <895000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "vcc_1v8_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vddshv5_sdio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "vpp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vcc_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &main_i2c1 { From 4a2c5dddf9e9049bfb3dde18657ee349131b0def Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 3 Oct 2023 14:41:34 +0530 Subject: [PATCH 36/48] arm64: dts: ti: k3-am62a7-sk: Enable audio on AM62A Add nodes for audio codec and sound card, enable the audio serializer (McASP1) under use and update pinmux. Reviewed-by: Jayesh Choudhary Reviewed-by: Devarsh Thakkar Link: https://www.ti.com/lit/zip/sprr459 Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20231003-mcasp_am62a-v3-5-2b631ff319ca@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 77 +++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 377ab823bbcc..8f64ac2c7568 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -125,6 +125,41 @@ led-0 { default-state = "off"; }; }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62Ax-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; }; &mcu_pmx0 { @@ -230,6 +265,15 @@ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ >; }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */ + AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */ + AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; }; &mcu_pmx0 { @@ -377,6 +421,19 @@ exp1: gpio@22 { "MCASP1_FET_SEL", "UART1_FET_SEL", "PD_I2C_IRQ", "IO_EXP_TEST_LED"; }; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + DVDD-supply = <&buck5>; + }; }; &sdhci1 { @@ -467,3 +524,23 @@ cpsw3g_phy0: ethernet-phy@0 { ti,min-output-impedance; }; }; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; From 69c570ebc3964534c19dc4438d3b96f55d489fc3 Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Tue, 3 Oct 2023 14:52:59 +0530 Subject: [PATCH 37/48] arm64: dts: ti: Fix HDMI Audio overlay in Makefile Apply HDMI audio overlay to AM625 and AM62-LP SK-EVMs DT binaries, instead of leaving it in a floating state. Fixes: b50ccab9e07c ("arm64: dts: ti: am62x-sk: Add overlay for HDMI audio") Reported-by: Rob Herring Signed-off-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20231003092259.28103-1-a-bhatia1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 51dab9499cd0..8bd5acc6d683 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,6 +9,8 @@ # alphabetically. # Boards with AM62x SoC +k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb @@ -19,7 +21,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-hdmi-audio.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-hdmi-audio.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb From 6ff2e5bb81895247f0414ff6b129c8e025b99a17 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 5 Oct 2023 20:43:01 +0530 Subject: [PATCH 38/48] arm64: dts: ti: k3-*: Convert DMSS to simple-bus "simple-mfd" as standalone compatible is frowned upon, so model DMSS (Data Movement Subsystem) node as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-2-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ac760d9b831d..e5c64c86d1d5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -82,7 +82,7 @@ audio_refclk1: clock-controller@82e4 { dmss: bus@48000000 { bootph-all; - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; dma-ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index c24ff905437f..fcbfb1b5242b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -42,7 +42,7 @@ gic_its: msi-controller@1820000 { dmss: bus@48000000 { bootph-all; - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; dma-ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 2e50030d09ad..0be642bc1b86 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -99,7 +99,7 @@ gic_its: msi-controller@1820000 { dmss: bus@48000000 { bootph-all; - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; dma-ranges; From 6507bfa7e0cde01c5feecdbc163b392021d15cbb Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 5 Oct 2023 20:43:02 +0530 Subject: [PATCH 39/48] arm64: dts: ti: k3-*: Convert NAVSS to simple-bus "simple-mfd" as standalone compatible is frowned upon, so model main and MCU NAVSS (Navigator SubSystem) nodes as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-3-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index bc460033a37a..d0c85eb3bb04 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -600,7 +600,7 @@ intr_main_gpio: interrupt-controller@a00000 { }; main_navss: bus@30800000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 1e536dc41f61..edd5cfbec40e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -185,7 +185,7 @@ mcu_timer3: timer@40430000 { }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index cdb1d6b2a982..264913f83287 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -91,7 +91,7 @@ main_gpio_intr: interrupt-controller@a00000 { }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 6ffaf85fa63f..ef13d64961ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -318,7 +318,7 @@ wkup_gpio1: gpio@42100000 { }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index f6c7e1614521..746b9f8b1c64 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -181,7 +181,7 @@ main_gpio_intr: interrupt-controller@a00000 { }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index fa8af20c7818..f7ab7719fc07 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -440,7 +440,7 @@ adc { }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 6d32544c8881..bbb4b7f81039 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -775,7 +775,7 @@ main_sdhci1: mmc@4fb0000 { }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 56504578c464..20a6a35ad61a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -443,7 +443,7 @@ mcu_spi2: spi@40320000 { }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; From 10c6c4db6283053e8ec20eef19eb77d4aeffed1a Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 10 Oct 2023 16:47:22 +0530 Subject: [PATCH 40/48] arm64: dts: ti: k3-j721s2-main: Add BCDMA instance for CSI2RX J721S2 has a dedicated BCDMA controller for the Camera Serial Interface. Events from the BCDMA controller instance are routed through the main UDMA interrupt aggregator as unmapped events. Add the node for the DMA controller and keep it disabled by default. See J721S2 Technical Reference Manual (SPRUJ28) for further details: http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Vaishnav Achath Reviewed-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20231010111723.17524-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index bbb4b7f81039..d7346385d010 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -807,6 +807,7 @@ main_udmass_inta: msi-controller@33d00000 { ti,sci = <&sms>; ti,sci-dev-id = <265>; ti,interrupt-ranges = <0 0 256>; + ti,unmapped-event-sources = <&main_bcdma_csi>; }; secure_proxy_main: mailbox@32c00000 { @@ -1103,6 +1104,22 @@ main_udmap: dma-controller@31150000 { ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + main_bcdma_csi: dma-controller@311a0000 { + compatible = "ti,j721s2-dmss-bcdma-csi"; + reg = <0x00 0x311a0000 0x00 0x100>, + <0x00 0x35d00000 0x00 0x20000>, + <0x00 0x35c00000 0x00 0x10000>, + <0x00 0x35e00000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <3>; + ti,sci = <&sms>; + ti,sci-dev-id = <225>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + status = "disabled"; + }; + cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x310d0000 0x0 0x400>; From 8b2e41833bd649086e32ac4c3a412d7ec80e8202 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 10 Oct 2023 16:47:23 +0530 Subject: [PATCH 41/48] arm64: dts: ti: k3-j784s4-main: Add BCDMA instance for CSI2RX J784S4 has a dedicated BCDMA controller for the Camera Serial Interface. Events from the BCDMA controller instance are routed through the main UDMA interrupt aggregator as unmapped events. Add the node for the DMA controller and keep it disabled by default. See J784S4 Technical Reference Manual (SPRUJ52) for further details: http://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath Reviewed-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20231010111723.17524-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index efed2d683f63..3123413e2140 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -703,6 +703,7 @@ main_udmass_inta: msi-controller@33d00000 { ti,sci = <&sms>; ti,sci-dev-id = <321>; ti,interrupt-ranges = <0 0 256>; + ti,unmapped-event-sources = <&main_bcdma_csi>; }; secure_proxy_main: mailbox@32c00000 { @@ -1000,6 +1001,22 @@ main_udmap: dma-controller@31150000 { ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + main_bcdma_csi: dma-controller@311a0000 { + compatible = "ti,j721s2-dmss-bcdma-csi"; + reg = <0x00 0x311a0000 0x00 0x100>, + <0x00 0x35d00000 0x00 0x20000>, + <0x00 0x35c00000 0x00 0x10000>, + <0x00 0x35e00000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <3>; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + status = "disabled"; + }; + cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x00 0x310d0000 0x00 0x400>; From dbf02264de7ab28933c152a2e5751f7ce9cd8c3d Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:51 +0530 Subject: [PATCH 42/48] arm64: dts: ti: k3-j721s2: Add ESM instances Patch adds the ESM instances for J721s2. It has 3 instances. One in the main domain and two in the mcu-wakeup domain. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-2-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 +++++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index d7346385d010..1ff1445f9d84 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1818,4 +1818,11 @@ c71_1: dsp@65800000 { firmware-name = "j721s2-c71_1-fw"; status = "disabled"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>; + bootph-pre-ram; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 20a6a35ad61a..cdb35223c144 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -695,4 +695,18 @@ mcu_r5fss0_core1: r5f@41400000 { ti,loczrama = <1>; }; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; }; From 1c4cc4ca5aff237544c502e6e5ffbe13f4c372fa Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:52 +0530 Subject: [PATCH 43/48] arm64: dts: ti: k3-j784s4: Add ESM instances Patch adds the ESM instances for J784s4. It has 3 instances. One in the main domain and two in the mcu-wakeup domain. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-3-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3123413e2140..568aade886e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1585,4 +1585,12 @@ c71_3: dsp@67800000 { firmware-name = "j784s4-c71_3-fw"; status = "disabled"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, + <695>; + bootph-pre-ram; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 4ab4018d3695..a7b5c4cb7d3e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -700,4 +700,18 @@ ospi1: spi@47050000 { status = "disabled"; }; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; }; From 81be795bb3eac1a8cdbd5adb862044c12dc2b744 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:53 +0530 Subject: [PATCH 44/48] arm64: dts: ti: k3-j7200: Add MCU domain ESM instance Patch adds the ESM instance for MCU domain of J7200. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-4-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ef13d64961ef..3fc588b848c6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -637,4 +637,11 @@ wkup_vtm0: temperature-sensor@42040000 { power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; From caae599de8c6cc7405dcfd3bcd66a467eee23d2b Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:54 +0530 Subject: [PATCH 45/48] arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances There are totally 19 instances of watchdog module. One each for the 8 A72 cores, one each for the 4 C7x cores, 1 for the GPU, 1 each for the 6 R5F cores in the main domain. The non-A72 instances are coupled with the R5Fs, C7x & GPU instances. Keeping them as reserved as they are not used by A72. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-5-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 198 +++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 568aade886e5..6ca80d16ee78 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1593,4 +1593,202 @@ main_esm: esm@700000 { <695>; bootph-pre-ram; }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2200000 0x00 0x100>; + clocks = <&k3_clks 348 1>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 348 0>; + assigned-clock-parents = <&k3_clks 348 4>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2210000 0x00 0x100>; + clocks = <&k3_clks 349 1>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 349 0>; + assigned-clock-parents = <&k3_clks 349 4>; + }; + + watchdog2: watchdog@2220000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2220000 0x00 0x100>; + clocks = <&k3_clks 350 1>; + power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 350 0>; + assigned-clock-parents = <&k3_clks 350 4>; + }; + + watchdog3: watchdog@2230000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2230000 0x00 0x100>; + clocks = <&k3_clks 351 1>; + power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 351 0>; + assigned-clock-parents = <&k3_clks 351 4>; + }; + + watchdog4: watchdog@2240000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2240000 0x00 0x100>; + clocks = <&k3_clks 352 1>; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 352 0>; + assigned-clock-parents = <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2250000 0x00 0x100>; + clocks = <&k3_clks 353 1>; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 353 0>; + assigned-clock-parents = <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2260000 0x00 0x100>; + clocks = <&k3_clks 354 1>; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 354 0>; + assigned-clock-parents = <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2270000 0x00 0x100>; + clocks = <&k3_clks 355 1>; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 355 0>; + assigned-clock-parents = <&k3_clks 355 4>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them reserved as these will be used by their + * respective firmware + */ + watchdog8: watchdog@22f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x22f0000 0x00 0x100>; + clocks = <&k3_clks 360 1>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 360 0>; + assigned-clock-parents = <&k3_clks 360 4>; + /* reserved for GPU */ + status = "reserved"; + }; + + watchdog9: watchdog@2300000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2300000 0x00 0x100>; + clocks = <&k3_clks 356 1>; + power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 356 0>; + assigned-clock-parents = <&k3_clks 356 4>; + /* reserved for C7X_0 DSP */ + status = "reserved"; + }; + + watchdog10: watchdog@2310000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2310000 0x00 0x100>; + clocks = <&k3_clks 357 1>; + power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 357 0>; + assigned-clock-parents = <&k3_clks 357 4>; + /* reserved for C7X_1 DSP */ + status = "reserved"; + }; + + watchdog11: watchdog@2320000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2320000 0x00 0x100>; + clocks = <&k3_clks 358 1>; + power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 358 0>; + assigned-clock-parents = <&k3_clks 358 4>; + /* reserved for C7X_2 DSP */ + status = "reserved"; + }; + + watchdog12: watchdog@2330000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2330000 0x00 0x100>; + clocks = <&k3_clks 359 1>; + power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 359 0>; + assigned-clock-parents = <&k3_clks 359 4>; + /* reserved for C7X_3 DSP */ + status = "reserved"; + }; + + watchdog13: watchdog@23c0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23c0000 0x00 0x100>; + clocks = <&k3_clks 361 1>; + power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 361 0>; + assigned-clock-parents = <&k3_clks 361 4>; + /* reserved for MAIN_R5F0_0 */ + status = "reserved"; + }; + + watchdog14: watchdog@23d0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23d0000 0x00 0x100>; + clocks = <&k3_clks 362 1>; + power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 362 0>; + assigned-clock-parents = <&k3_clks 362 4>; + /* reserved for MAIN_R5F0_1 */ + status = "reserved"; + }; + + watchdog15: watchdog@23e0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23e0000 0x00 0x100>; + clocks = <&k3_clks 363 1>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 0>; + assigned-clock-parents = <&k3_clks 363 4>; + /* reserved for MAIN_R5F1_0 */ + status = "reserved"; + }; + + watchdog16: watchdog@23f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23f0000 0x00 0x100>; + clocks = <&k3_clks 364 1>; + power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 364 0>; + assigned-clock-parents = <&k3_clks 364 4>; + /* reserved for MAIN_R5F1_1 */ + status = "reserved"; + }; + + watchdog17: watchdog@2540000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2540000 0x00 0x100>; + clocks = <&k3_clks 365 1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 365 0>; + assigned-clock-parents = <&k3_clks 366 4>; + /* reserved for MAIN_R5F2_0 */ + status = "reserved"; + }; + + watchdog18: watchdog@2550000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2550000 0x00 0x100>; + clocks = <&k3_clks 366 1>; + power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 366 0>; + assigned-clock-parents = <&k3_clks 366 4>; + /* reserved for MAIN_R5F2_1 */ + status = "reserved"; + }; }; From 9ac8006abcda58c0fd866f967b1a6a05aa3c6b48 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:55 +0530 Subject: [PATCH 46/48] arm64: dts: ti: k3-j784s4-mcu: Add the mcu domain watchdog instances There are totally 2 instances of watchdog module in MCU domain. These instances are coupled with the MCU domain R5F instances. Disabling them as they are not used by Linux. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-6-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index a7b5c4cb7d3e..adb5ea6b9732 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -714,4 +714,30 @@ wkup_esm: esm@42080000 { ti,esm-pins = <63>; bootph-pre-ram; }; + + /* + * The 2 RTI instances are couple with MCU R5Fs so keeping them + * reserved as these will be used by their respective firmware + */ + mcu_watchdog0: watchdog@40600000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40600000 0x00 0x100>; + clocks = <&k3_clks 367 1>; + power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 367 0>; + assigned-clock-parents = <&k3_clks 367 4>; + /* reserved for MCU_R5F0_0 */ + status = "reserved"; + }; + + mcu_watchdog1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40610000 0x00 0x100>; + clocks = <&k3_clks 368 1>; + power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 368 0>; + assigned-clock-parents = <&k3_clks 368 4>; + /* reserved for MCU_R5F0_1 */ + status = "reserved"; + }; }; From eb4c9909dc49f742bdbb9e5d411a4ac1df1cb6d6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:56 +0530 Subject: [PATCH 47/48] arm64: dts: ti: k3-j721s2-main: Add the main domain watchdog instances There are totally 9 instances of watchdog module. One each for the 2 A72 cores, one each for the 2 C7x cores, 1 for the GPU, 1 each for the 4 R5F cores in the main domain. Keeping only the A72 instances enabled and reserving the rest by default as they will be used by their respective firmware. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-7-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 1ff1445f9d84..b03731b53a26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1825,4 +1825,104 @@ main_esm: esm@700000 { ti,esm-pins = <688>, <689>; bootph-pre-ram; }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2200000 0x00 0x100>; + clocks = <&k3_clks 286 1>; + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 286 1>; + assigned-clock-parents = <&k3_clks 286 5>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2210000 0x00 0x100>; + clocks = <&k3_clks 287 1>; + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 287 1>; + assigned-clock-parents = <&k3_clks 287 5>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them reserved as these will be used by their + * respective firmware + */ + watchdog2: watchdog@22f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x22f0000 0x00 0x100>; + clocks = <&k3_clks 290 1>; + power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 290 1>; + assigned-clock-parents = <&k3_clks 290 5>; + /* reserved for GPU */ + status = "reserved"; + }; + + watchdog3: watchdog@2300000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2300000 0x00 0x100>; + clocks = <&k3_clks 288 1>; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 288 1>; + assigned-clock-parents = <&k3_clks 288 5>; + /* reserved for C7X_0 */ + status = "reserved"; + }; + + watchdog4: watchdog@2310000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2310000 0x00 0x100>; + clocks = <&k3_clks 289 1>; + power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 289 1>; + assigned-clock-parents = <&k3_clks 289 5>; + /* reserved for C7X_1 */ + status = "reserved"; + }; + + watchdog5: watchdog@23c0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23c0000 0x00 0x100>; + clocks = <&k3_clks 291 1>; + power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 291 1>; + assigned-clock-parents = <&k3_clks 291 5>; + /* reserved for MAIN_R5F0_0 */ + status = "reserved"; + }; + + watchdog6: watchdog@23d0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23d0000 0x00 0x100>; + clocks = <&k3_clks 292 1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 292 1>; + assigned-clock-parents = <&k3_clks 292 5>; + /* reserved for MAIN_R5F0_1 */ + status = "reserved"; + }; + + watchdog7: watchdog@23e0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23e0000 0x00 0x100>; + clocks = <&k3_clks 293 1>; + power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 293 1>; + assigned-clock-parents = <&k3_clks 293 5>; + /* reserved for MAIN_R5F1_0 */ + status = "reserved"; + }; + + watchdog8: watchdog@23f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23f0000 0x00 0x100>; + clocks = <&k3_clks 294 1>; + power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 294 1>; + assigned-clock-parents = <&k3_clks 294 5>; + /* reserved for MAIN_R5F1_1 */ + status = "reserved"; + }; }; From 56bc311585206a8955de793301d4f84fb4ad2ee6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Sun, 8 Oct 2023 10:16:57 +0530 Subject: [PATCH 48/48] arm64: dts: ti: k3-j712s2-mcu: Add the mcu domain watchdog instances There are totally 2 instances of watchdog module in MCU domain. These instances are coupled with the MCU domain R5F instances. Reserving them as they are not used by A72. Signed-off-by: Keerthy Link: https://lore.kernel.org/r/20231008044657.25788-8-j-keerthy@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index cdb35223c144..7254f3bd3634 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -709,4 +709,30 @@ wkup_esm: esm@42080000 { ti,esm-pins = <63>; bootph-pre-ram; }; + + /* + * The 2 RTI instances are couple with MCU R5Fs so keeping them + * reserved as these will be used by their respective firmware + */ + mcu_watchdog0: watchdog@40600000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40600000 0x00 0x100>; + clocks = <&k3_clks 295 1>; + power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 295 1>; + assigned-clock-parents = <&k3_clks 295 5>; + /* reserved for MCU_R5F0_0 */ + status = "reserved"; + }; + + mcu_watchdog1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40610000 0x00 0x100>; + clocks = <&k3_clks 296 1>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 1>; + assigned-clock-parents = <&k3_clks 296 5>; + /* reserved for MCU_R5F0_1 */ + status = "reserved"; + }; };