apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets

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We want the BIOS to setup the EILVT APIC registers. The offsets
were hardcoded and BIOS settings were overwritten by the OS.
Now, the subsystems for MCE threshold and IBS determine the LVT
offset from the registers the BIOS has setup. If the BIOS setup
is buggy on a family 10h system, a workaround enables IBS. If
the OS determines an invalid register setup, a "[Firmware Bug]:
" error message is reported.

We need this change also for upcomming cpu families.

Signed-off-by: Robert Richter <robert.richter@amd.com>
LKML-Reference: <1286360874-1471-3-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

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Robert Richter 2010-10-06 12:27:54 +02:00 • committed by Ingo Molnar

parent a68c439b19

commit 27afdf2008

4 changed files with 154 additions and 41 deletions

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4

arch/x86/include/asm/apic.h

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19

arch/x86/kernel/apic/apic.c

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27

arch/x86/kernel/cpu/mcheck/mce_amd.c

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145

arch/x86/oprofile/op_model_amd.c

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