drm/i915: Make sure we respect n.max on VLV

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We limit the maximum n divider value in order to make sure the PLL's
reference inout is at least 19.2 MHz. I assume that is done to satisfy
some hardware requirement.

However we never check whether that calculated limit is below the
maximum supoorted N divider value (7). In practice that is always true
since we only support 100 MHz reference clock, but making the code
safe against higher reference clocks seems like a reasoanble thing to
do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-09-24 21:26:24 +03:00 • committed by Daniel Vetter

parent c1a9ae4388

commit 27e639bf02

1 changed files with 3 additions and 2 deletions

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drivers/gpu/drm/i915/intel_display.c

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