clk: sunxi-ng: h6: fix bus clocks' divider position

Browse source

The bus clocks (AHB/APB) on Allwinner H6 have their second divider start
at bit 8, according to the user manual and the BSP code. However,
currently the divider offset is incorrectly set to 16, thus the divider
is not correctly read and the clock frequency is not correctly calculated.

Fix this bit offset on all affected bus clocks in ccu-sun50i-h6.

Cc: stable@vger.kernel.org # v4.17.y
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

...

This commit is contained in:

Icenowy Zheng 2018-08-09 01:19:52 +08:00 • committed by Chen-Yu Tsai

parent 5b394b2ddf

commit 2852bfbf4f

1 changed files with 4 additions and 4 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

8

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

View file