drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

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Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Rodrigo Vivi 2013-05-06 19:37:37 -03:00 • committed by Daniel Vetter

parent 891348b2bf

commit 285541647a

2 changed files with 11 additions and 0 deletions

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7

drivers/gpu/drm/i915/i915_reg.h

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4

drivers/gpu/drm/i915/intel_pm.c

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