drm/i915/cx0: Compute plls for MTL+ platform

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To bring MTL+ platform aligned call and calculate PLL state
from dpll framework.

v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
    The state is computed either for a C10 or on the PTL port B eDP
    over TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
    "non_tc_phy" instead of "c10phy".

    Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
    symmetry with mtl_compute_non_tc_phy_dpll().
v3: Reword commit message (Suraj)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-19-mika.kahola@intel.com

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Mika Kahola 2025-11-17 12:45:48 +02:00

parent d174cfb51d

commit 28d5533f27

1 changed files with 69 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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