drm/msm/dsi: Populate PLL 10nm clock ops

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Populate PLL clock ops from downstream. This contains the VCO PLL
ops and the registration of standard clk_divider and clk_mux clocks.
Unlike 14nm PLL, the postdividers/mux of the slave PLL doesn't need
to be set to the same values of the postdivs/mux of the master PLL.
Hence, we don't need special postdivider clock ops like we did with
the 14nm PLL driver.

Like the previous PLL drivers, the implementation is slightly different
from downstream. We don't use shadow clocks, but have the ability to
reparent the RCGs to a different source.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

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Archit Taneja 2018-01-17 11:35:26 +05:30 • committed by Rob Clark

parent 973e02db35

commit 28e4309ab9

1 changed files with 654 additions and 8 deletions

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drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c

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