drm/tegra: sor: Registers are 32-bit

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Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2015-01-26 16:02:48 +01:00

parent 28c23373b8

commit 28fe207600

1 changed files with 6 additions and 7 deletions

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drivers/gpu/drm/tegra/sor.c

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