usb: dwc2: Properly account for the force mode delays

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When a force mode bit is set and the IDDIG debounce filter is enabled,
there is a delay for the forced mode to take effect. This delay is due
to the IDDIG debounce filter and is variable depending on the platform's
PHY clock speed. To account for this delay we can poll for the expected
mode.

On a clear force mode, since we don't know what mode to poll for, delay
for a fixed 100 ms. This is the maximum delay based on the slowest PHY
clock speed.

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

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John Youn 2016-09-07 19:39:43 -07:00 • committed by Felipe Balbi

parent fef6bc37db

commit 2938fc63e0

1 changed files with 14 additions and 17 deletions

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drivers/usb/dwc2/core.c

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