net/mlx5e: Support SWP-mode offload L4 csum calculation

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Calculate the pseudo-header checksum for both IPSec transport mode and
IPSec tunnel mode for mlx5 devices that do not implement a pure hardware
checksum offload for L4 checksum calculation. Introduce a capability bit
that identifies such mlx5 devices.

Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://lore.kernel.org/r/20240613210036.1125203-7-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

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Rahul Rameshbabu 2024-06-14 00:00:36 +03:00 • committed by Jakub Kicinski

parent fac15a72b8

commit 296eaab825

3 changed files with 44 additions and 2 deletions

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37

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h

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6

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h

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3

include/linux/mlx5/mlx5_ifc.h

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