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ARMv7 compliant cache maintenance for the decompressor

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On v7 and later cores, cache maintenance operations by set/way are only
 intended to be used in the context of on/offlining a core, while it has
 been taken out of the coherency domain. Any use intended to ensure that
 the contents of the cache have made it to main memory is unreliable,
 since cacheline migration and non-architected system caches may cause
 these contents to linger elsewhere, without being visible in main memory
 once the MMU and caches are disabled.
 
 So switch to cache maintenance by virtual address for v7 and later cores.
 This makes the 32-bit kernel bootable on systems with L3 system caches
 that are not covered by set/way operations, such as Socionext SynQuacer.
 
 Tony says:
 
   I gave these a try on top of the earlier "arm: fix Kbuild issue caused
   by per-task stack protector GCC plugin" and booting still works for
   me on armv7 including appended dtb:
 
   Tested-by: Tony Lindgren <tony@atomide.com>
 
 Linus says:
 
   No problem, I have tested it on the following:
 
   - ARMv7 Cortex A9 x 2 Qualcomm APQ8060 DragonBoard
   - ARM PB11MPCore (4 x 1176)
   - ARMv7 Ux500 Cortex A9 x 2
 
   The PB11MPCore is again the crucial board, if it work on that
   board it works on anything, most of the time :D
 
   Tested-by: Linus Walleij <linus.walleij@linaro.org>
 
 Note that the first 2 patches are shared with the efi/core branch in
 TIP, which is the reason why this is sent as a pull request rather
 than via the patch system.
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Merge tag 'arm32-efi-cache-ops-for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux into devel-stable

ARMv7 compliant cache maintenance for the decompressor

On v7 and later cores, cache maintenance operations by set/way are only
intended to be used in the context of on/offlining a core, while it has
been taken out of the coherency domain. Any use intended to ensure that
the contents of the cache have made it to main memory is unreliable,
since cacheline migration and non-architected system caches may cause
these contents to linger elsewhere, without being visible in main memory
once the MMU and caches are disabled.

So switch to cache maintenance by virtual address for v7 and later cores.
This makes the 32-bit kernel bootable on systems with L3 system caches
that are not covered by set/way operations, such as Socionext SynQuacer.

Tony says:

  I gave these a try on top of the earlier "arm: fix Kbuild issue caused
  by per-task stack protector GCC plugin" and booting still works for
  me on armv7 including appended dtb:

  Tested-by: Tony Lindgren <tony@atomide.com>

Linus says:

  No problem, I have tested it on the following:

  - ARMv7 Cortex A9 x 2 Qualcomm APQ8060 DragonBoard
  - ARM PB11MPCore (4 x 1176)
  - ARMv7 Ux500 Cortex A9 x 2

  The PB11MPCore is again the crucial board, if it work on that
  board it works on anything, most of the time :D

  Tested-by: Linus Walleij <linus.walleij@linaro.org>

Note that the first 2 patches are shared with the efi/core branch in
TIP, which is the reason why this is sent as a pull request rather
than via the patch system.
This commit is contained in:
Russell King 2020-03-12 11:15:29 +00:00
commit 29a843aec0
1 changed files with 86 additions and 76 deletions
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