drm/radeon: allocate PPLLs from low to high

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The order shouldn't matter, but there have been problems
reported on certain older asics.  This behaves more
like the original code before the PPLL allocation
rework.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc:  Markus Trippelsdorf <markus@trippelsdorf.de>

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Alex Deucher 2012-10-05 10:22:02 -04:00

parent cd23492af3

commit 29dbe3bcd2

1 changed files with 4 additions and 4 deletions

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8

drivers/gpu/drm/radeon/atombios_crtc.c

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