can: mcp251xfd: add support for internal PLL

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The PLL is enabled if the configured clock is less than or equal to 10 times
the max clock frequency.

The device will operate with two different SPI speeds. A slow speed determined
by the clock without the PLL enabled, and a fast speed derived from the
frequency with the PLL enabled.

Link: https://lore.kernel.org/all/20220207131047.282110-16-mkl@pengutronix.de
Link: https://lore.kernel.org/all/20201015124401.2766-3-mas@csselectronics.com
Co-developed-by: Magnus Aagaard Sørensen <mas@csselectronics.com>
Signed-off-by: Magnus Aagaard Sørensen <mas@csselectronics.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

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This commit is contained in:

Marc Kleine-Budde 2020-10-16 22:36:39 +02:00

parent 445dd72a6d

commit 2a68dd8663

2 changed files with 75 additions and 20 deletions

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88

drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c

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7

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

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