drm/i915/skl: Read the Memory Latency Values for WM computation

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This patch reads the memory latency values for all the 8 levels for
SKL. These values are needed for the Watermark computation.

v2: Incorporated the review comments from Damien on register
    indentation.

v3: Updated the code to use the sandybridge_pcode_read for reading
    memory latencies for GEN9.

v4: Don't put gen 9 in the middle of an ordered list of ifs
    (Damien)

v5: take the rps.hw_lock around sandybridge_pcode_read() (Damien)

v6: Use gen >= 9 in the pcode_read() function for data1.
    Move the defines near the gen6 ones and prefix them with PCODE.
    Remove unused timeout define (the pcode_read() code has a larger
    timeout already).

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Pradeep Bhat 2014-11-04 17:06:38 +00:00 • committed by Daniel Vetter

parent 5fad84a753

commit 2af30a5c40

3 changed files with 83 additions and 6 deletions

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6

drivers/gpu/drm/i915/i915_drv.h

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7

drivers/gpu/drm/i915/i915_reg.h

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76

drivers/gpu/drm/i915/intel_pm.c

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