clk: renesas: r9a08g046: Add USB2.0 clock and reset entries

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Add module clock and reset definitions for the USB2.0 interfaces on the
RZ/G3L (r9a08g046) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260616104459.410743-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2026-06-16 11:44:45 +01:00 • committed by Geert Uytterhoeven

parent 182b03cbe8

commit 2bbc0f34ef

1 changed files with 15 additions and 0 deletions

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drivers/clk/renesas/r9a08g046-cpg.c

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