From 2c3ed158087d2971cad00faab24e2143eef49944 Mon Sep 17 00:00:00 2001 From: Lu Yao Date: Tue, 8 Sep 2026 13:52:02 +0800 Subject: [PATCH] drm/amd/display: Fix wrong plane index in dcn6 writeback latency loop Use plane_descriptors[k] for the loop bound, matching the loop body. Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6") Reviewed-by: George Zhang Signed-off-by: Lu Yao Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c index 78bdf11d0d46..6ad41846a73a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c @@ -1304,7 +1304,7 @@ void dcn6_calculate_watermarks_and_dram_speed_change_support( DML_LOG_VERBOSE("DML::%s: k=%u, VActiveLatencyHidingUs = %f\n", __func__, k, p->VActiveLatencyHidingUs[k]); } - for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[j].stream_index].writeback.active_writebacks_per_stream; ++j) { + for (unsigned int j = 0; j < p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream; ++j) { double byte_per_pixel_luma_in_buffer = 1.0; double buffer_for_luma = (double)p->WritebackInterfaceBufferSize * 1024.0 / 2.0; if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[j].pixel_format == dml2_444_64) {