staging: axis-fifo: Correct handling of tx_fifo_depth for size validation

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Remove erroneous subtraction of 4 from the total FIFO depth read from
device tree. The stored depth is for checking against total capacity,
not initial vacancy. This prevented writes near the FIFO's full size.

The check performed just before data transfer, which uses live reads of
the TDFV register to determine current vacancy, correctly handles the
initial Depth - 4 hardware state and subsequent FIFO fullness.

Fixes: 4a965c5f89 ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core")
Cc: stable@vger.kernel.org
Signed-off-by: Gabriel Shahrouzi <gshahrouzi@gmail.com>
Link: https://lore.kernel.org/r/20250419012937.674924-1-gshahrouzi@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Gabriel Shahrouzi 2025-04-18 21:29:37 -04:00 • committed by Greg Kroah-Hartman

parent 98698ca0e5

commit 2ca34b5087

1 changed files with 0 additions and 3 deletions

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drivers/staging/axis-fifo/axis-fifo.c

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