drm/i915/pvc: Update forcewake domain for CCS register ranges

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The bspec was just updated with a correction to the forcewake domain
required when accessing registers in the CCS engine ranges (0x1a000 -
0x1ffff and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
the RENDER domain, not the GT domain.

Bspec: 67609
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014233004.1053678-1-matthew.d.roper@intel.com

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Matt Roper 2022-10-14 16:30:04 -07:00

parent 21f213e67e

commit 2d3093fd5e

1 changed files with 12 additions and 10 deletions

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drivers/gpu/drm/i915/intel_uncore.c

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