dmaengine: hsu: correct use of channel status register

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[ Upstream commit 4f4bc0abff ]

There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.

Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.

Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.

Fixes: 2b49e0c567 ("dmaengine: append hsu DMA driver")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>

...

This commit is contained in:

Andy Shevchenko 2016-03-18 14:26:32 +02:00 • committed by Sasha Levin

parent be851fafe2

commit 2d6e463198

2 changed files with 4 additions and 1 deletions

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2

drivers/dma/hsu/hsu.c

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3

drivers/dma/hsu/hsu.h

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