From 2d8a8ae673070edfcd79e6a9b92f0067c57cf7b8 Mon Sep 17 00:00:00 2001 From: YuBiao Wang Date: Thu, 24 Sep 2026 14:55:26 +0800 Subject: [PATCH] drm/amdgpu: skip MGCG programming on a VF for gfx v12_1 MGCG registers are PF-only. Skip programming them under SR-IOV. Signed-off-by: Jane Jian Signed-off-by: YuBiao Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index f8901e9e3086..1cf175aac4de 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2433,8 +2433,10 @@ static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask return r; } - gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, false, - xcc_id, true); + /* MGCG is device wide and owned by the PF */ + if (!amdgpu_sriov_vf(adev)) + gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, false, + xcc_id, true); /* GFX CGCG and LS is disabled by rlc fw */ gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); @@ -2456,8 +2458,9 @@ static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask if (r) return r; } - gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, true, - xcc_id, true); + if (!amdgpu_sriov_vf(adev)) + gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, true, + xcc_id, true); } return 0;