ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA

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Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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Marek Vasut 2019-06-28 02:19:44 +02:00 • committed by Dinh Nguyen

parent 325ec920ee

commit 2dbaa6a6dc

1 changed files with 6 additions and 2 deletions

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arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts

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