From 2ddf6752cd6a9f136b656fe1939687bff010f288 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Fri, 18 Sep 2026 16:31:19 +0800 Subject: [PATCH] drm/amdgpu/mes12: gate gfx pipe reset on PER_PIPE Replace the disabled pipe-reset stub with the shared PER_PIPE capability check, so GFX MMIO pipe reset follows gfx_supported_reset. Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ef644a593a2f..bee8933eade5 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -424,13 +424,6 @@ int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, return 0; } -static bool mes_v12_0_pipe_reset_support(struct amdgpu_device *adev) -{ - /* Disable the pipe reset until the CPFW fully support it.*/ - dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); - return false; -} - /* Use MES callbacks directly while holding the MES lock. */ static int mes_v12_0_restore_gfx_kernel_queue(struct amdgpu_device *adev, u32 me, u32 pipe, u32 guilty_queue, @@ -499,7 +492,7 @@ static int mes_v12_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, uint32_t reset_pipe, clean_pipe; int i; - if (!mes_v12_0_pipe_reset_support(adev)) + if (!amdgpu_gfx_me_pipe_reset_supported(adev)) return -EOPNOTSUPP; amdgpu_gfx_rlc_enter_safe_mode(adev, 0);