clk: tegra: Make sor_safe the parent of dpaux and dpaux1

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It turns out that sor_safe, rather than pll_p, is the parent of the
dpaux and dpaux1 clocks.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2016-06-23 12:52:30 +02:00

parent 2858038696

commit 2e34c2ac16

1 changed files with 2 additions and 2 deletions

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4

drivers/clk/tegra/clk-tegra210.c

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