drm/i915: Implement chv display PHY lane stagger setup

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Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by:  Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2015-04-10 18:21:27 +03:00 • committed by Daniel Vetter

parent ac935a8b6d

commit 2e523e98bb

3 changed files with 79 additions and 4 deletions

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13

drivers/gpu/drm/i915/i915_reg.h

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35

drivers/gpu/drm/i915/intel_dp.c

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35

drivers/gpu/drm/i915/intel_hdmi.c

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