spi: dt-bindings: adi,axi-spi-engine: add multi-lane support

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Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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David Lechner 2026-01-23 14:37:29 -06:00 • committed by Mark Brown

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commit 2e706f86a5

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Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml

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