drm/radeon/hdmi: DCE3: clean ACR control

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What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

This has been tested for possible regressions on DCE3 HD3470 (RV620).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Rafał Miłecki 2014-05-16 11:10:29 +02:00 • committed by Alex Deucher

parent 8f33a156c2

commit 2e93cac90c

2 changed files with 7 additions and 3 deletions

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8

drivers/gpu/drm/radeon/r600_hdmi.c

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2

drivers/gpu/drm/radeon/r600d.h

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