dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility

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This cache controller is also used on the ESWIN EIC7700 SoC.
However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
So add dedicated compatible string for it.

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Pritesh Patel 2025-03-20 16:24:44 +05:30 • committed by Conor Dooley

parent 0af2f6be1b

commit 2eb6836615

1 changed files with 41 additions and 3 deletions

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Documentation/devicetree/bindings/cache/sifive,ccache0.yaml vendored

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