riscv: Enable generic clockevent broadcast

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When percpu-timers are stopped by deep power saving mode, we
need system timer help to broadcast IPI_TIMER.

This is first introduced by broken x86 hardware, where the local apic
timer stops in C3 state. But many other architectures(powerpc, mips,
arm, hexagon, openrisc, sh) have supported the infrastructure to
deal with Power Management issues.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

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Guo Ren 2021-03-07 10:24:46 +08:00 • committed by Palmer Dabbelt

parent 9530141455

commit 2f100585d0

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2

arch/riscv/Kconfig

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16

arch/riscv/kernel/smp.c

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