iommu/vt-d: Enable 5-level paging mode in the PASID entry

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If the CPU has support for 5-level paging enabled and the IOMMU also
supports 5-level paging then enable the 5-level paging mode for first-
level translations - used when SVM is enabled.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

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Sohil Mehta 2017-12-20 11:59:27 -08:00 • committed by Joerg Roedel

parent f1ac10c24e

commit 2f13eb7c58

1 changed files with 13 additions and 2 deletions

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15

drivers/iommu/intel-svm.c

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