drm/amd/display: Fix assertion due to disable/enable CM blocks

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[why]
Some dc state transitions can result in CM blocks being disabled, then
re-enabled.  The disable will set a defer bit, but re-enable will not
clear it.  When optimizing later, an assert will be hit due to incorrect
expected HW state.

[how]
Clear defer bits if the block is re-enabled before optimization is
executed.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Aric Cyr 2026-05-05 16:27:29 -04:00 • committed by Alex Deucher

parent b11107cb63

commit 2f28f0063a

3 changed files with 5 additions and 0 deletions

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3

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

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1

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

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1

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

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