ARM: dts: ti/omap: dra7: fix PCIe PHY clock divider definition

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Commit d0bdd8bb7f ("ARM: dts: ti/omap: dra7: fix redundant
clock divider definition") removes the clock divider definition
from optfclk_pciephy_div, reasoning that the table is redundant,
as it contains the values 1 and 2, while also setting ti,max-div
to 2 while ti,min-div is implicitly initialized to 1.

What that commit missed was the fact that the values in the table
are in reverse order, i.e. first 2, then 1.

As is clearly described in the documentation, the ordering is
signifficant, the actual values for the register setting are
derived from the index. If no table is specified, the driver
assumes that the register value is divider - 1 (see also `_get_val`
in `drivers/clk/ti/divider.c`).

What is in fact redundant is the value of ti,max-div that is
derived from the table if none is specified. To satisfy device
tree semantic linters, it is removed instead.

Fixes: d0bdd8bb7f ("ARM: dts: ti/omap: dra7: fix redundant clock divider definition")
Signed-off-by: David Oberhollenzer <david.oberhollenzer@sigma-star.at>
Link: https://patch.msgid.link/20260716113947.92513-1-david.oberhollenzer@sigma-star.at
Signed-off-by: Kevin Hilman (TI) <khilman@baylibre.com>

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This commit is contained in:

David Oberhollenzer 2026-07-16 13:39:47 +02:00 • committed by Kevin Hilman (TI)

parent cee9395acd

commit 2fabd2f406

1 changed files with 1 additions and 1 deletions

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arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi

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