irqchip/gic-v3-its: Enable cacheable attribute Read-allocate hints

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Read-allocation hints are not enabled for both the GIC-ITS and GICR
tables. This forces the hardware to always read the table contents
from an external memory (DDR) which is slow compared to cache memory.
Most of the tables are often read by hardware. So, it's better to
enable Read-allocate hints in addition to Write-allocate hints in
order to improve the GICR_PEND, GICR_PROP, Collection, Device, and
vCPU tables lookup time.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

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Shanker Donthineni 2017-01-25 21:51:41 -06:00 • committed by Marc Zyngier

parent f20cc9b00c

commit 2fd632a003

1 changed files with 5 additions and 5 deletions

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drivers/irqchip/irq-gic-v3-its.c

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